The advent of ever more powerful computer systems has resulted in a continuing search for ways to reduce power consumption and increase performance in the systems.
Dynamic power consumption and performance are directly proportional to the frequency of the clock in complimentary metal oxide semiconductor (CMOS) circuits. In low power/high performance applications, there exists a necessary trade off between power and performance. Traditionally, a single clock frequency is chosen for a particular application, which determines the specific power/performance ratio for that application. Typically, the ratio is balanced in favor of performance.
Clocks are periodic signals used for timing and synchronization in synchronous digital circuits. The clock frequency defines the period of time in which logic operations are performed. Logic operations in electronic circuits proceed through a series, or path, of logic gates. The results of different paths of logic operations are generally converged with the results of other paths of logic operations. The results of different paths must be converged at a time when all of the paths have completed processing data through the logic gates and have a result. Because different logic paths do not process data in the same amount of time, those logic paths that finish processing first must hold the result of their logic operations until all the logic paths are to converge have completed processing.
Clocks are used in digital processors to synchronize the holding of logic operation results until all logic paths have completed processing. The time it takes for all logic paths that are to be converged to finish processing is defined as a clock cycle. When all the data from all the logic paths has been converged, the logic paths can then be used to process the next pieces of data. A clock event generates a rising, or source clock edge that typically initiates the start of processing new data through the logic paths. A second clock event follows the clock event that generated the rising clock edge that generates a destination, or falling clock edge. The values in all the logic paths are sampled at the destination clock edge to determine if new values have been processed that can be converged. Each microprocessor only has a limited amount of capacity, so any time and power used to operate clocks to perform their regulating function is time and power that cannot be used to perform processing functions. It is therefore desirable that clocks perform their function as efficiently as possible. Traditionally, a single clock frequency is chosen for a particular application that will enable the clocks to function efficiently while minimizing the impact on performance.
A continuing search has been directed to the development of a method and apparatus that will enable the operating system to dynamically change the clock frequency. By enabling the system to fine-tune the clock speed based on load requirements of the system, the overall energy requirements can be minimized while system performance is optimized.